Course Outcomes:
After completion of this course, students will be able to:
C6EE3.01-1 Describe the basics of computer architecture and its organization
C6EE3.01-2 Recognize processor models based on their organization, addressing modes and instruction set
C6EE3.01-3 Explain basics of ALU, control unit and computer organization such as memory & I/O
C6EE3.01-4 Differentiate between various architectures based on performance, cost and applicability
C6EE3.01-5 Summarize impact of modern techniques like pipelining, express buses processor performance
Mapping Matrix of CO's and PO's
COs |
PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PO7 |
PO8 |
PO9 |
PO10 |
PO11 |
PO12 |
PSO 1 |
PSO 2 |
C6EE3-01.1: |
2 |
2 |
2 |
2 |
3 |
- |
- |
- |
- |
- |
- |
3 |
3 |
3 |
C6EE3-01.2: |
2 |
2 |
2 |
2 |
3 |
- |
- |
- |
- |
- |
- |
3 |
3 |
3 |
C6EE3-01.3: |
2 |
2 |
2 |
2 |
3 |
- |
- |
- |
- |
- |
- |
3 |
3 |
3 |
C6EE3-01.4: |
2 |
2 |
2 |
2 |
3 |
- |
- |
- |
- |
- |
- |
3 |
3 |
3 |
C6EE3-01.5: |
2 |
2 |
2 |
2 |
3 |
- |
- |
- |
- |
- |
- |
3 |
3 |
3 |